TASIC Design Manager (Image Signal Processor) THE ROLE: AMD Image Signal Processor (ISP) team has immediate opening of ASIC design manager. The successful candidate will be working with global teams and lead local design team to develop ISP IP and deliver to AMD SoC projects. THE PERSON: The candidate would be hired in as design manager, with the expectation that he/she would have minimal 5 years of RTL design experience and 3 years of management experience in the multimedia, image processing or similar industry. KEY RESPONSIBILITIES: • Lead ISP hardware IP development from spec. to tape out • Lead and mentor design team to solve all technical issues during project development • Guide and review design spec. and micro architecture with team members and keep the design and implementation in sync with overall architecture • Establish project database management, methodology, design flow and guideline; enforce good engineering discipline and improve team's efficiency and effectiveness • Interface with other functional teams, such as algorithm, verification and firmware to resolve interdisciplinary issues and coordinate the task and schedule • Daily management of design team EXPERIENCE AND SKILLS: • BS-CS/BS-EE with at least 10 years' experience or MS with at least 8 years' experience in ASIC/SoC design • Strong multimedia/video/camera related system level knowledge and experience • In depth knowledge and experience of ASIC design flow is required, which include RTL coding (guideline, style, database management), simulation, FPGA verification, synthesis, timing closure, power estimation, power domain design, formal verification; successful tapeout and validation experience is a must • Experience of working with multi-site teams is preferred ACADEMIC CREDENTIALS: • Bachelor or Master, major in EE, CS or related area LOCATION: • Shanghai, Pudong, Zhangjiang